A novel dynamic threshold static power optimization algorithm is presented.

With the development of VLSI manufacture technology and the higher integration degree, test power consumption has become one of the main concerns of IC designers.

There are three serious problems: These are test application time, test data volume, and test power consumption.

As CMOS device dimensions have been down to the very deep-submicron, test power is higher than the power produced in circuit s work period.

The test power dissipation is one of the critical facts which should be considered carefully when designing the SoC for testability,so a parallel boundary scan TAM and its test controller are proposed.

Experiments on ISCAS\'89 benchmark circuits have shown an average reduction of 55% in test data volumes and an average reduction of 52% in the test application time compared with the serial scan method;meanwhile,the average test power dissipations can be ignored.

Combined with the structure character of Random Access Scan(RAS),this new test group is optimized,which solves the problems such as test data volume,test power dissipation,and test time.

The software power optimization scheme was experimentally validated on a wide range of embedded software rou.

In this paper, a method of power optimization based on form of design of switch-capacitance circuit is proposed.

Since much work has been done on power optimization techniques at all stage of the design process, this paper mainly study on how to reduce the power dissipation in logic stage of circuit design.