1.
Research and Design of All-digital PLL with High Frequency and Low Jitter Performance;
高速低抖动全数字锁相环的设计研究
2.
Design of all digital phase locked loop based on FPGA
基于FPGA的全数字锁相环的设计
3.
Research on Adpll-Basedtime Digital Converter
基于全数字锁相环的时间数字转换器的研究
4.
Research on All Digital Phase-Locked Loop with High Precision Automatic Modulus Control;
高精度自动变模控制全数字锁相环的研究
5.
A New Low Power All-Digital PLL Design Based on VHDL
基于VHDL的一种低功耗新型全数字锁相环设计
6.
Automatic Modulus Controlled All Digital Phase Locked Loop with Large Lock-in Range
一种自动变模控制的宽频带全数字锁相环
7.
FPGA-based high-performance all-digital phase-locked loop design
基于FPGA的高性能全数字锁相环设计与实现
8.
A New Type ADPLL Used in High-Frequency Induction Pyrogenation System
全数字锁相环高频感应加热系统的设计
9.
A Novel All-digital Phase-locked Loop Z-domain Model in Time Domain
一种新型的时间域全数字锁相环Z域模型
10.
Realization of all-digital PLL based on VHDL
一种基于VHDL语言的全数字锁相环的实现
11.
Design and Realization of the High Speed ADPLL Based on the 65nm Process
基于65nm工艺的超高速全数字锁相环的设计和实现
12.
Study on Key Techniques of Digital Up/Down Conversion and Digital Phase-Lock-Loop;
数字上下变频及全数锁相环关键技术研究
13.
The Design of Digital Circuits in CMOS Charge-Pump Phase-Locked Loop;
CMOS电荷泵锁相环中的数字电路设计
14.
APPLICATION OF ISPLSI1016 IN DIGITAL PHASE-LOCKED LOOP;
ispLSI1016在数字锁相环中的应用
15.
Detetion of Harmonic Waves Based on DPLL Synchronous Sampling
基于数字锁相环同步采样的谐波检测
16.
Design of Digital Phase Locked Loop Used in SDH Equipment Clock
SDH设备时钟中的数字锁相环设计
17.
The Implementation and Analysis of Digital Phase-locked Loop Based on FPGA
基于FPGA的数字锁相环实现与性能分析
18.
Improvement and Application of Digital Costas Phase-locked Loop
数字Costas锁相环的改进及应用