1.
The fact that the constructed networks canfinish minimum Hamming distance decoding and minimum soft distance decoding to graphtheoretic code was proved.
最后给出采用所构造的前向神经网络进行一个图论码的硬判决译码和软判决译码的计算机模拟结果。
2.
Research on Iterative Soft-Decision Decoding of LDPC and GLD Codes;
LDPC码和GLD码的软判决迭代译码研究
3.
Research Encoding and Decoding of RS Codes and the Application of Soft-Decision Decoding;
RS码编译码方法及软判决译码应用的研究
4.
A Design and FPGA Implementation of (2, 1, 9) Soft-Decision Viterbi Decoder;
（2，1，9）软判决Viterbi译码器的设计与FPGA实现
5.
Software Decision Decoding of Fano Decoding Algorithm and the FPGA Implementation Method of Its Decoder
软判决Fano译码算法的FPGA实现
6.
Distributed Soft-decision Decoding of Reed-Solomon Codes Based on Cooperative Network;
基于协作网的RS码分布式软判决译码算法
7.
Algebraic soft decision decoding algorithm for Reed-Solomon codes based on Chase algorithm
一种基于Chase的RS码代数软判决译码算法
8.
Research on Reliability-Based Soft-Decision Decoding Algorithms for Linear Block Codes
基于可靠性的线性分组码软判决译码算法研究
9.
Digital AGC input-matching circuit for soft-decision LDPC Decoders
基于AGC方法的软判决LDPC译码器输入匹配电路
10.
On a New Class of Two-Dimension Error-Correcting Codes and Their Soft-Decision Decoding Algorithms;
一种新型二维纠错码及其软判决译码方法的研究
11.
A Decoding Algorithm Based on Joint judging message passing schedule for Low-Density Parity Check Codes
基于联合判决消息传递机制的LDPC码译码算法研究
12.
Bit-Interleaved Coded Modulation with Iterative Decoding Using Soft Decision
基于软判决反馈迭代译码的比特交织编码调制方案
13.
The Decoding Research and Hardware Implementation of LDPC Codes Based on FPGA;
基于FPGA的LDPC码译码研究与硬件实现
14.
The Research of Turbo Code and Hardware Design;
Turbo码编译码研究及其硬件设计
15.
Principles of the Codec for LDPC Codes and Its Hardware Implementation;
LDPC码编译码器的原理及其硬件实现
16.
The Hardware Design of Concatenated Decoder Based on FPGA
基于FPGA的级联码的译码器的硬件设计
17.
Research on the Implementation of CCSDS-RS(255,223) High Speed Decoder
CCSDS-RS(255,223)码高速译码器的硬件实现研究
18.
The Implementation of BCH Hardware Decoder on BM Algorithm
基于BM算法的BCH码的译码硬件实现