1.
Design and Analysis of CMOS PLL Clock Generator;
CMOS锁相环时钟发生器的设计与研究
2.
Study and Design of a Lower-Voltage, Lower-Power, Higher-Stability CMOS Phase Locked Loop;
低电压低功耗高稳定性CMOS锁相环的研究与设计
3.
Design of Novel Fully-differential Charge Pump for PLL;
锁相环用新型全差分CMOS电荷泵设计
4.
The Research and Design of CMOS Charge-Pump Phase-Locked Loop;
CMOS电荷泵锁相环的研究与设计
5.
The Design of Digital Circuits in CMOS Charge-Pump Phase-Locked Loop;
CMOS电荷泵锁相环中的数字电路设计
6.
Design of PLL Frequency Synthesizer Based on CMOS Techniques;
基于CMOS工艺的锁相环频率合成器设计
7.
Design and Analysis of CMOS Integration CPPLL;
CMOS集成电荷泵锁相环的设计与研究
8.
The Research and Design of CMOS High-powered Electric Charge Pump PLL;
CMOS高性能电荷泵锁相环的研究与设计
9.
622MHz Charge Pump PLL Design of Basing on CMOS Technics;
基于CMOS工艺的622MHz电荷泵锁相环设计
10.
800MHz-1.2GHz CMOS Adaptive PLL Design;
800MHz-1.2GHz CMOS变带宽自适应锁相环设计
11.
A Design of Charge-Pump Phase Lock Loop Based on CMOS Technics
基于CMOS工艺的电荷泵锁相环的设计
12.
Design of 622MHz CPPLL Based on 0.18μm CMOS Technology
0.18μm CMOS工艺622MHz电荷泵锁相环设计
13.
Design of a 1.2 GHz PLL Based on 0.35 μm CMOS Technology
一种基于0.35μm CMOS工艺的1.2GHz锁相环
14.
Design of PLL for CMOS 434/868 MHz FSK/OOK Transmitter
用于434/868MHz FSK/OOK CMOS发射机的锁相环设计
15.
Design of 2.5GHz CPPLL Based on 0.18μm CMOS Process
基于0.18μm CMOS工艺2.5GHz电荷泵锁相环的设计
16.
An Improved CMOS Charge Pump PLL design
一个改进型CMOS电荷泵锁相环的设计
17.
Design of a CMOS Charge-Pump PLL and Investigation of the Phase Noise;
CMOS电荷泵锁相环的设计及相位噪声的研究
18.
The Design and Implementation of Charge Pump Phase-Locked Loop Based on 0.18μm CMOS Process;
基于0.18μm CMOS工艺电荷泵锁相环的设计与实现