1.
Design of the Module-2N+1 Synchronous Counter with Cyclic-Code;
2N+1进制同步循环码计数器设计
2.
Design of Codec for Quasi-cyclic LDPC Codes and Its FPGA Implementation
准循环LDPC码的编译码器设计及FPGA实现
3.
Design of LDPC Coder-Decoder Based on Cyclic Shift Matrices
应用循环移位矩阵设计LDPC码译码器
4.
Design of Novel Cyclic Shift Permutation Structure for Quasi-Cyclic LDPC Codes Decoder
适用于准循环LDPC码译码器的新型循环移位置换结构设计
5.
Design and Implementation of Decoder for Quasi-Cyclic Low-Density Parity-Check Codes;
准循环低密度校验码译码器的设计与实现
6.
Design of Quasi-Cyclic LDPC Code Families Based on Algebraic Method and Matrix Transformation
基于代数构造和矩阵变换的准循环LDPC码组设计
7.
Modulation Parameter Estimation Based on Cyclic Spectrum of MPSK
基于循环谱的相位编码信号调制参数估计
8.
Numerical Solver for the National Cycle Program
国家循环计划的数字解算器
9.
CP-to-binary code converter
循环排列码－二进制码转换器
10.
FPGA Decoder Implementation for Quasi-Cyclic Low-Density Parity-Check Codes;
准循环低密度校验码译码器的FPGA实现
11.
Symbol Based Circular State Turbo Code and its Decoder
基于符号的循环状态Turbo码及其解码器
12.
An 800Mbps Quasi-Cyclic LDPC Encoder Implementation with FPGA
800Mbps准循环LDPC码编码器的FPGA实现
13.
An FPGA Implementation of QC-LDPC Decoder
准循环LDPC码译码器的FPGA实现
14.
Cyclic Codes over F_2+uF_2 of Length 2n
环F_2+uF_2上长度为2n(n为奇数)的循环码
15.
High throughput in-system programmable quasi cyclic LDPC encoder architecture
在线可编程准循环LDPC码高速编码器结构
16.
Cyclotomic Number and the Minimum Distance of a Class of Binary Cyclic Codes
分圆数与一类二元循环码的最小距离
17.
VLSI decoding design of low-density parity-check codes based on circulant matrices
基于循环矩阵的低密度校验码的VLSI译码设计
18.
Research on Cyclic Code and Constacyclic Code over Ring F_2+uF_2;
环F_2+uF_2上的循环码和常循环码的研究