1.
Analysis on the Output Sequences of Clock Control Generator and Application in Spread Spectrum Communication;
钟控生成器输出序列的特性分析及其在扩频通信中的应用
2.
Correlation Analysis on Several Stop-and-Go Clocked Keystream Generators;
对几类钟控停走生成器的相关性分析
3.
MADL Based Cycle Accurated Simulator Generation;
基于MADL语言的时钟精确级仿真器生成
4.
The version was raised successfully. It may take 15 minutes or more for this information to replicate to all domain controllers.
此版本提升成功。至少需要 15 分钟将此信息复制到所有的域控制器。
5.
The functionality was raised successfully. It may take 15 minutes or more for this information to replicate to all domain controllers.
此功能提升成功。至少需要 15 分钟将此信息复制到所有的域控制器。
6.
boosted-high level clock generator
升压高电平时钟发生器
7.
TV station clock mark generator
电视台时钟台标发生器
8.
DRCG Direct Rambus clock generator
直接RAMBUS时钟发生器
9.
single-phase clock generator
单相时钟脉冲发生器
10.
Clock Setting and Time Controlling of PLC;
可编程控制器的时钟设立及时间控制
11.
clock pulse generator
时钟脉冲发生器同步脉冲发生器
12.
The operation has completed successfully. It may take 15 minutes or more for this information to replicate to all domain controllers.
操作已成功完成。要将该信息复制到所有域控制器需要花十五分钟或更长的时间。
13.
These rhythms are regulated by the biological clock, which includes an input pathway, a central oscillator, an output pathway and a gateway.
高等植物的生物钟系统由输入途径、中央振荡器、输出途径以及一个阀门效应器组成。
14.
This counter displays the number of universal group membership evaluations per second on a global catalog domain controller from non-global catalog domain controllers.
此计数器显示来自非全局编录域控制器的全局编录域控制器上每秒钟通用组成员身份列举的次数。
15.
Design and Analysis of CMOS PLL Clock Generator;
CMOS锁相环时钟发生器的设计与研究
16.
Design and Implementation of Wideband High-Performance TIADC Clock Generator
一种宽带高性能TIADC时钟发生器
17.
Scheme of Fast Self-Calibration for a FPGA Chip Clock Generator
FPGA片上时钟发生器快速自校准方案
18.
Finally, the time delay compensation controller is designed for NCS when the controller is event-driven.
最后,研究了控制器为时钟驱动时网络控制系统的时延补偿控制。