1.
Applications of Combined Karnaugh Map in Analysis of Logic Circuits
联合卡诺图在逻辑电路分析中的应用
2.
On the Application of Hypo-state Karnaugh Map in the Analysis and Design of Time-Sequence Logic Circuit;
次态卡诺图在时序逻辑电路分析和设计中的运用
3.
"Analysis" Design Combination of Logic Circuits;
用“分析法”设计组合逻辑电路的探讨
4.
Implementation of Flip-flop Circuit within Digital Logic Analyzer Based on FPGA;
数字逻辑分析仪中触发电路的FPGA实现
5.
The Analysis and Design of the Pulse Asynchronous Tune Sequencing Logic Circuit;
脉冲异步时序逻辑电路的分析与设计探讨
6.
An Automated Soft Error Rate Analysis Platform for Combinational Logic Circuits
组合逻辑电路的软错误率自动分析平台
7.
Analysis of Open-phase Fault
输电线路非全相再故障保护动作逻辑的分析
8.
The analysis and designation on the assembly logic circuit is one of the important content of digital circuit.
组合逻辑电路的分析设计是数字电路重点内容之一。
9.
Improvement of Back Logic Circuit of IC Test System and Research of Analog Delay Line Capability;
集成电路测试系统后逻辑支持电路改进与模拟延迟线性能分析
10.
Analysis and design of high linearity current reference for current mode circuits
电流模逻辑电路中高线性度电流参考源的分析与设计(英文)
11.
low-level current mode logic
低电平电流型逻辑电路
12.
distributed josephson logic circuit
分布参数约瑟夫孙逻辑电路
13.
resistor transistor logic
电阻-晶体管逻辑电路
14.
IC logic control
集成电路逻辑电磁控制
15.
TTL [Transistor-Transistor Logic]
电晶体-电晶体逻辑线路
16.
Analysis of Protection Logistic for Last Breaker Trip in Zhengping Converter Station
政平换流站最后断路器保护逻辑分析
17.
emitter follower logic circuit
发射极跟随器逻辑电路
18.
AGTL+ Assisted Gunning Transceiver Logic
援助发射接收逻辑电路