1.
Design of multi-valued double-edge-triggered D flip-flop based on clock-controlled neuron MOS transistor
基于钟控神经MOS管的多值双边沿D触发器设计
2.
Design of low power Flip-Flop based on double edge trigger;
基于双边沿触发的低功耗触发器逻辑设计
3.
edge-triggered bistable circuit
边沿触发双稳态电路
4.
Novel current-mode CMOS quaternary edge-triggered flip-flops
新型电流型CMOS四值边沿触发器设计
5.
positive edge clock
正边沿触发时钟脉冲
6.
Furthermore,the proposed construction can be easily extended to the design of multiple valued edge triggered flip flop with a higher radix.
此外 ,该设计结构极易推广至基值更高的多值边沿触发器的设计
7.
A Research on the Operating Characterictics of Master-slave JK Flip-flop Cosisting of TTL NAND Gates in Rise and Fall Edges of CP;
由与非门构成的主从JK触发器在CP边沿工作特性研究
8.
The Design of a SEE Hardened D Flip-Flop
一种抗单粒子全加固D触发器的设计
9.
Design and Analysis of SEU/SET Hardened D Flip-Flop
SEU/SET加固D触发器的设计与分析
10.
inner-triggering dualtrace sampling oscilloscope
内触发双踪取样示波器
11.
bipolar flip-flop
双极型半导体触发器
12.
Using D Trigger to Add Inquiring Interface for TPC-1 Experiment System s A/D Transform Experiment;
利用D触发器为TPC—1实验系统的A/D转换实验增加查询式接口
13.
bistable trigger element
双稳(态)触发元件[触发器](螺旋桨)叶素，叶片
14.
Design of Set-Reset D Flip-Flop Using Resonant Tunneling 1-of-2 MUX
基于1-of-2共振隧穿数据选择器的可置位复位D触发器设计
15.
flip flop circuit
双稳态多谐振荡器触发电路
16.
clocked flip flop
时标触发器定时触发器
17.
A DET shift counter designed with the DET shift register is demonstrated.
使用该移位寄存器设计双边沿移位计数器的实例被演示。
18.
A Pulse-Train Generator Based on DIAC
基于双向触发二极管的脉冲序列发生器